¡ Semiconductor
MSM80C48/49/50, MSM80C35/39/40
FUNCTIONAL DESCRIPTION
Added Functions of MSM80C48, MSM80C49 and MSM80C50
The MSM80C48, MSM80C49 and MSM80C50 are basically incorporated with the capabilities of
Intel's 8048, 8049, and 8050 plus the following new functions:
1. Power-Down Mode Enhancements
1.1 Power-down by software
(1) Clock (See item 4, "Power-down mode", for details.)
a. Crystal oscillator halt (HLTS instruction)
Power requirements can be minimized.
b. Clock supply halt (HALT instruction)
Restart is accomplished without oscillator wait.
(2) I/O ports
I/O port floating instructions
Power consumption resulting from inputs/outputs can be minimized with FLT and FLTT
instructions.
Port floating is cancelled by executing FRES instruction, "0" level at INT pin or "0" level at
RESET pin.
(3) Six types of power-down can be done by a combination of HLTS/HALT and FLT/FLTT
instructions.
1.2 Power-down by hardware (See 4.3, Power-down mode by V pin utilization for
DD
details.)
Crystal oscillators can be halted by controlling the V pin, thereby floating all I/O ports
DD
for minimum power consumption.
2. Additional Instructions (11)
HLTS
MOV A, P2
HALT
FLT
FLTT
MOVP1, @ R3
MOVP1 P, @R3
DEC @Rr
FRES
DJNZ @ Rr, addr
MOV A, P1
3. Improved Uses of BUS P - , P1 - , P2 - , and SS pins
0 7
0 7
0 7
3.1 BUS P -
0 7
The MSM80C48, MSM80C49, and MSM80C50 remove the limitation on the use of OUTL
BUS, A instructions during the external ROM access mode by having an independent data
latch and external ROM mode address latch in BUS P - .
0 7
Consequently, there is no need to relocate bus port instructions when in the external ROM
access mode.
3.2 P - and P2 -
10 7
0 7
TheMSM80C48,MSM80C49andMSM80C50aredesignedtominimizepowerconsumption
when P1 - and P2 - are used as input/output ports, to maximize the performance of
0 7
0 7
CMOS.
When these ports are used as output ports, the acceleration circuit is actuated only when
14/20
OKI [ OKI ELECTRONIC COMPONETS ]
