欢迎访问ic37.com |
会员登录 免费注册
发布采购

MSM80C40 参数 Datasheet PDF下载

MSM80C40图片预览
型号: MSM80C40
PDF下载: 下载PDF文件 查看货源
内容描述: 8位CMOS微控制器 [CMOS 8-Bit Microcontroller]
分类和应用: 微控制器
文件页数/大小: 20 页 / 149 K
品牌: OKI [ OKI ELECTRONIC COMPONETS ]
 浏览型号MSM80C40的Datasheet PDF文件第12页浏览型号MSM80C40的Datasheet PDF文件第13页浏览型号MSM80C40的Datasheet PDF文件第14页浏览型号MSM80C40的Datasheet PDF文件第15页浏览型号MSM80C40的Datasheet PDF文件第16页浏览型号MSM80C40的Datasheet PDF文件第17页浏览型号MSM80C40的Datasheet PDF文件第19页浏览型号MSM80C40的Datasheet PDF文件第20页  
¡ Semiconductor  
MSM80C48/49/50, MSM80C35/39/40  
4.3 Hardware power-down mode  
In the MSM80C48, MSM80C49 and MSM80C50, forcing the level at the V  
pin to a "0"  
DD  
during either external ROM or internal ROM mode results in suspension of the oscillator  
function and subsequent floating (high impedance) of all the I/O pins except the RESET,  
SS and XTAL 1/2 pins. The CPU is thereby stopped while maintaining internal status.  
4.4 Cancellation of hardware power-down mode  
(1) Use of RESET pin  
m
The clock generator is activated and the CPU started up when a "1" level is applied to  
the V pin while a "0" level is input to the RESET pin. If this "0" level is kept applied  
DD  
to the RESET pin until oscillation become stable, the CPU will be reset and will start  
executing from address 0.  
(2) Use of the INT pin during external interrupt enable status (i.e. following execution of EN  
I instruction)  
m
The clock generator is activated and the CPU started up when a "1" level is applied to  
the V  
pin while a "0" level is applied to the INT pin. If this "0" level is maintained  
DD  
until the occurrence of at least 2 ALE output signals, an external interrupt is generated,  
and execution starts from address 3.  
However, if the power-down mode is started during an interrupt processing routine,  
execution will be continued on the next instruction after the present instruction.  
(3) Use of the INT pin during external interrupt disable mode (i.e. following excution of DIS  
I instruction or hardware reset)  
m
The clock generator is activated and the CPU started up when a "1" level is applied to  
the V pin while a "0" level is applied to the INT pin. If this "0" level is maintained  
DD  
until the occurrence of at least 2 ALE output signals, execution is continued on the next  
instruction after the present instruction.  
(4) Use of V  
pin only  
DD  
m
The clock generator is activated and the CPU started up when a "1" level is applied to  
the V pin while a "1" level is also applied to both the RESET and INT pins. In this  
DD  
case, execution is resumed from the stopped position.  
18/20  
 复制成功!