¡ Semiconductor
MSM7702-01/02/03
TIMING DIAGRAM
PCM Data Input/Output Timing
Transmit Timing
BCLK
XSYNC
1
2
3
4
5
6
7
8
9
10
11
tXS
tSX
tWS
tXD1
tSD
MSD
tXD2
D3
tXD3
D8
PCMOUT
D2
D4
D5
D6
D7
When tXS £ 1/2 • Fc, the Delay of the MSD bit is defined as tXD1
When tSX £ 1/2 • Fc, the Delay of the MSD bit is defined as tSD
.
.
Receive Timing
BCLK
1
2
3
4
5
6
7
8
9
10
11
tRS
tSR
tWS
RSYNC
PCMIN
tDS
tDH
MSD
D2
D3
D4
D5
D6
D7
D8
13/17