PEDL9090-02
¡ Semiconductor
ML9090-01,-02
Output pin, I/O Pin and Register States When Reset is Input
Pin and register states while the RESET input is pulled to a “L” level are listed below.
Output pin, I/O pin
State
DI/O
Input state
"L" (VSS
Oscillating state
"L" (VSS
KREQ
OSC2
)
R0 to R4
)
PBA
High impedance
High impedance
PB0 to PB7 (for ML9090-01)
SEG1 to SEG80
"L" (VSS
"L" (VSS
"L" (VSS
)
)
)
COM1 to COM10 (for ML9090-01)
COM1 to COM18 (for ML9090-02)
Register
Key scan register
Display data register
X address register
Y address register
Port A register
State
Reset to "0"
Display data is retained
Reset to "0"
Reset to "0"
Reset to "0"
Port B register
Reset to "0"
Control register 1
Control register 2
No change from value prior to reset input
Display OFF
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