PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
(10) Busy flag and address counter read (Execution time is 1 ms.)
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Instruction code
H
L
BF O6 O5 O4 O3 O2 O1 O0
The busy flag (BF) is output by this instruction to indicate whether the ML9040A-Axx/
-Bxx is engaged in internal operations (BF = "H") or not (BF = "L").
When BF = "H", no new instruction is accepted. It is therefore necessary to verify BF =
"L" before inputting a new instruction.
When BF = "L", a correct address counter value is output. The address counter value
must match the DD RAM address or CG RAM address. The decision of whether it is
a DD RAM address or CG RAM address is made by the address previously set.
SincetheaddresscountervaluewhenBF="H"issometimesincrementedordecremented
by 1 during internal operations, it is not always a correct value.
(11) DD RAM and CG RAM data read
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Instruction code
H
H
P7 P6 P5 P4 P3 P2 P1 P0
Character codes (bits P to P ) are read from the DD RAM, while character patterns (P
7
7
0
to P ) from the CG RAM.
0
Selection of DD RAM or CG RAM is decided by the address previously set.
After reading those data, the address counter (ADC) is incremented or decremented by
1 as set by the shift mode mentioned in item "(3) shift mode set".
The execution time, when the OSC oscillation frequency is 270 kHz, is 37 ms.
(Note) Conditions for the reading of correct data:
1 When the DD RAM address set or CG RAM address set is input before
inputting this instruction.
2 When the cursor/display shift is input before inputting this instruction in
case the character code is read.
3 Data after the second reading from RAM when read more than 2 times.
Correct data is not output in any other case.
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