PEDL9040A-03
¡ Semiconductor
ML9040A-Axx/-Bxx
Generate biases externally and input them to V , V , V , V , V , and V .
DD
1
2
3
4
5
When the number of biases is 4, input the same potential to V and V . The execution
2
3
time, when the OSC oscillation frequency is 270 kHz, is 37 ms.
(7) CG RAM address setting
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Instruction code
L
L
L
H
C5 C4 C3 C2 C1 C0
When CG RAM addresses, bits C to C (binary), are set, the CG RAM is specified, until
5
0
the DD RAM address is set.
Write/read of the character pattern to and from the CPU begins with addresses, bits C
5
to C , starting from CG RAM selection.
0
The execution time, when the OSC oscillation frequency is 270 kHz, is 37 ms.
(8) DD RAM address setting
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Instruction code
L
L
H
D6 D5 D4 D3 D2 D1 D0
When the DD RAM addresses D to D (binary) are selected, the DD RAM is specified
6
0
until the DD RAM address is set.
Write/read of the character code to and from the CPU begins with addresses D to D
6
0
starting from DD RAM selection.
In the 1-line display mode (N = H), however, D to D (binary) must be set to one of the
6
0
values among "00" to "4F" (hex.).
Likewise, in the 2-line mode, D to D (binary) must be set to one of the values among
6
0
"00" to "27" (hex.) or "40" to "67" (hex.).
When any value other than the above is input, it is impossible to make a normal write/
read of character codes to and from the DD RAM.
The execution time, when the OSC oscillation frequency is 270 kHz, is 37 ms.
(9) DD RAM and CG RAM data write
R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Instruction code
L
H
E7 E6 E5 E4 E3 E2 E1 E0
When E to E (binary) codes are written to the DD RAM or CG RAM, the cursor and
7
0
display move as described in "(5) Cursor and display shift". The execution time, when
the OSC oscillation frequency is 270 kHz, is 37 ms.
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