¡ Semiconductor
ML9041
RS
1
0
RS
R/W
E
Busy
(Internal operation)
No
Busy
DB
DB
DB
DB
DB
DB
DB
DB
7
IR
7
Busy
DR7
6
5
4
3
2
IR
IR
IR
IR
IR
IR
IR
6
5
4
3
2
ADC
ADC
ADC
ADC
ADC
ADC
ADC
6
DR
DR
DR
DR
DR
DR
DR
6
5
4
3
2
5
4
3
2
1
0
1
0
1
1
0
0
Writing In IR
(Instruction
Register)
Reading BF (Busy Flag)
and ADC (Address Counter)
Writing In DR
(Data Register)
Figure 2 8-Bit Data Transfer
RS
RS
1
0
R/W
E
Busy
(Internal operation)
No
Busy
DB
DB
DB
DB
7
6
5
4
IR
IR
IR
IR
7
6
5
4
IR
IR
IR
IR
3
2
1
0
Busy
ADC
3
DR
DR
DR
DR
7
6
5
4
DR3
DR2
DR1
DR0
ADC6
ADC2
ADC5
ADC1
ADC4
ADC0
Writing In IR
(Instruction
Register)
Reading BF (Busy Flag)
and ADC (Address Counter)
Writing In DR
(Data Register)
Figure 3 4-Bit Data Transfer
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