¡ Semiconductor
ML9041
I/F with CPU
Parallel interface mode
The ML9041 can transfer either 8 bits once or 4 bits twice on the data bus for interfacing with any
8–bit or 4–bit microcontroller (CPU).
1) 8–bit interface data length
The ML9041 uses all of the 8 data bus lines DB0 to DB7 at a time to transfer data to and from the
CPU.
2) 4–bit interface data length
The ML9041 uses only the higher–order 4 data bus lines DB to DB twice to transfer 8–bit data
4
7
to and from the CPU.
The ML9041 first transfers the higher–order 4 bits of 8–bit data (DB to DB in the case of 8–bit
4
7
interface data length) and then the lower–order 4 bits of the data (DB to DB in the case of 8–bit
0
3
interface data length).
The lower–order 4 bits of data should always be transferred even when only the transfer of the
higher–order 4 bits of data is required. (Example: Reading the Busy Flag)
Two transfers of 4 bits of data complete the transfer of a set of 8–bit data. Therefore, when only
one access is made, the following data transfer cannot be completed properly.
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