PEDL87V21071-01
OKI Semiconductor
ML87V21071
2.6.3 Synch. Signal Generation Adjustment Setting (for Demonstration)
SUB_ADDRESS=78h (W/R): Output system memory control mode setting
DATA_BIT
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
Register name
HSSEL
ISYNC
SUB_ADDRESS=79h(W/R): OHS generation start position setting
DATA_BIT
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
2
BIT1
1
BIT0
0
SHSDL
Register name
7
6
5
4
3
ISYNC Initial value: 0; Setting range: 0 to 1
Sets the generation of an OVS/OHS internal Sync. signal.
* Since this is a setting for demonstration, normally set this bit to 0.
Table R2-6-3(1) Internal Sync. Signal Generation Setting
ISYNC
OVS, OHS output
0
Input (IVS, IHS)-delay output
Internally generated output
1
HSSEL Initial value: 0; Setting range: 0 to 1
Sets internally generated OHS composite Sync.
* Since this is a setting for demonstration, normally set this bit to 0.
Table R2-6-3(2) Internally Generated OHS Composite Sync Setting
HSSEL
OHS phase
Horizontal Sync. signal
Composite Sync
0
1
SHSDL[7:0] Initial value: 0011_1111; Setting range: 0000_0001 to 1111_1111
Set an OHS generation starting position of the internal Sync generator.
* Since this is a setting for demonstration, normally set this bit to 0.
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