PEDL87V21071-01
OKI Semiconductor
ML87V21071
2.6 Other Settings
2.6.1 Other Mode Settings
SUB_ADDRESS = 72h(W/R): Other settings
DATA_BIT
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
(Reserved) (Reserved)
(Reserved)
Register name
RLTG
PAOS
OEINV OUTDS PASS
PASS Initial value: 0; Setting range: 0 to 1
Sets data through mode.
The input pin is directly connected to the output pin. At this time, there is a delay generated equal to the
time it takes for the output data to pass through the internal circuitry.
Table R2-6-1 (1) Data Through Mode Setting
PASS
Mode
0
Normal operation
Data through
1
OUTDS Initial value: 0; Setting range: 0 to 1
Sets to disable forcibly all outputs.
Table R2-6-1 (2) All Outputs Disable Setting
OUTDS
All output pins
Dependent on other settings (OE, INT)
Disable
0
1
OEINV Initial value: 0; Setting range: 0 to 1
Sets OE input pin polarity inversion.
Table R2-6-1(3) OE Input Pin Polarity Inversion Setting
OEINV
OE input pin
0
OE = 0: Output data disable
OE = 1: Output data disable
1
PAOS Initial value: 0; Setting range: 0 to 1
Sets a starting offset of vertical valid data.
Table R2-6-1(4) Vertical Valid Data Starting Offset Setting
PAOS
Offset
No offset
0
1
2H (INPR = 0)/4H (INPR = 1)
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