FEDL7033-02
ML7033
1
Semiconductor
ABSOLUTE MAXIMUM RATINGS
Parameter
Power Supply Voltage
Analog Input Voltage
Digital Input Voltage
Storage Temperature
Symbol
VDD
VAIN
VDIN
TSTG
Condition
VDDD, VDDA
Rating
–0.3 to +7.0
–0.3 to VDD+0.3
–0.3 to VDD+0.3
–55 to +150
Unit
V
V
V
°C
—
—
—
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
Operating Temperature
High Level Input Voltage
Low Level Input Voltage
Symbol
VDD
TOP
VIH
VIL
Condition
Voltage to be fixed; VDDD, VDDA
—
Min.
Typ.
5.0
—
—
—
Max.
Unit
V
°C
V
4.75
–40
2.2
0
5.25
+85
VDD
0.8
All digital input pins
V
MCK = 2.048 MHz
–0.01% 2048 +0.01% kHz
–0.01% 4096 +0.01% kHz
MCKSEL (CR0-B5) bit = “0”
MCK Frequency
FMCK
MCK = 4.096 MHz
MCKSEL (CR0-B5) bit = “1”
BCLK Frequency
Sync Pulse Frequency
Clock Duty Ratio
Digital Input Rise Time
Digital Input Fall Time
MCK to BCLK Phase Difference
FBCLK
FSYNC
DCLK
tIR
tIF
tMB
tXS
tSX
tRS
tSR
BCLK
XSYNC, RSYNC
MCK,BCLK
256
–0.01%
40
—
8
4096
+0.01% kHz
kHz
50
—
—
—
—
—
—
—
60
50
50
50
—
—
—
—
%
ns
ns
ns
ns
ns
ns
ns
—
—
—
50
50
50
50
All digital input pins
MCK, BCLK
BCLK to XSYNC
XSYNC to BCLK
BCLK to RSYNC
RSYNC to BCLK
Transmit Sync Pulse Setting Time
Receive Sync Pulse Setting Time
XSYNC, RSYNC
125 µs –
1 BCLK
210
—
—
µs
SHORT (CR0-B4) bit = “0”
1BCLK
Sync Pulse Width
tWS
XSYNC, RSYNC
SHORT (CR0-B4) bit = “0”
1BCLK
ns
PCMOUT Set-up Time
PCMOUT Hold Time
tDS
tDH
RDL
CDL1
CDL2
CSG
PCMOUT
PCMOUT
Pull-up Resistor, PCMOUT
PCMOUT
50
50
0.5
—
—
0.1
—
—
—
—
—
—
—
—
—
50
50
—
ns
ns
kΩ
pF
pF
µF
Digital Output Load
Other output pins
SGC to AG
Bypass Capacitor for SGC
7/51
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