FEDL7033-02
ML7033
1
Semiconductor
Pin
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Symbol
VDDD
MCK
BCLK
DG
PCMIN
PCMOSY
PCMOUT
XSYNC
RSYNC
RESET
N.C
N.C
PDN
TEST
DG
BSEL1
ALM1
DET1
E0_1
F0_1
F1_1
F2_1
SWC1
VDDD
Type
—
I
I
—
I
O
O
I
I
I
Description
Power Supply for Internal Digital Circuit
Master Clock (2.048/4.096 MHz)
PCM Data Shift Clock
Digital Ground
PCM Data Input
PCM Data Output Indicator for Time-Slot Assignment
PCM Data Output
Transmit Synchronizing Clock Input
Receive Synchronizing Clock Input
Reset for Control Register
(Leave unconnected)
(Leave unconnected)
Power-down Control
LSI Manufacturer’s Test Input (keep logic “0”)
Digital Ground
Output for SLIC1 Battery Select
Input from SLIC1 Thermal Shut Down Alarm Detector
Input from SLIC1 Switch Hook, Ground Key or Ring Trip Detector
Output for SLIC1 Detector Mode Selection
Mode Control Output to SLIC1 F0
—
—
I
I
—
O
I
I
O
O
O
O
O
—
—
I
Mode Control Output to SLIC1 F1
Mode Control Output to SLIC1 F2
Output for SLIC1 Uncommitted Switch Control
Power Supply for Internal Digital Circuit
Power Supply for Internal Analog Circuit
CH1 Transmit Op-amp Input Positive
(Leave unconnected)
VDDA
AIN1P
N.C
—
Note: In this datasheet, “1” and “2” in names for pins which respectively exist for CH1 and CH2 are often
substituted by “n” (in a small letter).
Ex) GSX1, GSX2
AOUT1N, AOUT2N
DET1, DET2
→ GSXn
→ AOUTnN
→ DETn
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