6.8
6.9
Port 5 (P5) ................................................................................................... 6-19
Port 6 (P6) ................................................................................................... 6-21
6.10 Port 7 (P7) ................................................................................................... 6-23
6.11 Port 8 (P8) ................................................................................................... 6-25
6.12 Port 9 (P9) ................................................................................................... 6-27
6.13 Port 10 (P10) ............................................................................................... 6-29
6.14 Port 11 (P11) ............................................................................................... 6-31
6.15 Port 12 (P12) ............................................................................................... 6-32
Chapter 7 Output Pin Control Pin (OE)
Chapter 8 Clock Generation Circuit
Chapter 9 Time Base Counter (TBC)
9.1
1/n Counter .................................................................................................... 9-2
Chapter 10 Watchdog Timer (WDT)
10.1 WDT Control Register (WDTCON) .............................................................. 10-1
10.2 Operation of WDT ........................................................................................ 10-1
10.3 Time until Overflow of WDT ......................................................................... 10-2
10.4 Program Runaway Detection Timing Diagram ............................................ 10-2
Chapter 11 Flexible Timer (FTM)
11.1 Configuration of Counter Part ...................................................................... 11-6
11.2 Counter Selection Part................................................................................. 11-8
11.3 Type A1 Register Modules (TMR0–TMR3) ............................................... 11-10
11.3.1 Configuration of Type A1 Register Modules (TMR0–TMR3) ................ 11-10
[1] Timer Registers (TMR0, TMR0L–TMR3, TMR3L) .................................. 11-10
[2] Capture Control Register (CAPCON) ..................................................... 11-11
[3] Event Control Registers (EVNTCONL, EVNTCONH)............................. 11-12
[4] Event Dividing Counters 0–3 (EVDV0–EVDV3) ..................................... 11-14
[5] EVDV0–EVDV3 Buffer Registers (EVDV0BF–EVDV3BF) ..................... 11-14
11.3.2 Operation of Type A1 Register Modules (TMR0–TMR3) ..................... 11-15
11.3.3 Capture Pin Dividing Circuit.................................................................. 11-16
[1] Configuration of Dividing Circuit ............................................................. 11-16
[2] Operation of Dividing Circuit ................................................................... 11-16
[3] Operation to Switch Dividing Ratio ......................................................... 11-16
Contents-4
OKI [ OKI ELECTRONIC COMPONETS ]
