Chapter 3 CPU Architecture
3.1 Memory Space............................................................................................... 3-1
3.1.1 Memory Space Expansion .......................................................................... 3-1
3.1.2 Program Memory Space ............................................................................. 3-2
[1] Accessing Program Memory Space ........................................................... 3-4
[2] Vector Table Area....................................................................................... 3-4
[3] VCAL Table Area........................................................................................ 3-6
[4] ACAL Area .................................................................................................. 3-7
3.1.3 Data Memory Space ................................................................................... 3-8
[1] Special Function Register (SFR) Area........................................................ 3-9
[2] Expanded Special Function Register (Expanded SFR) Area ..................... 3-9
[3] Internal RAM Area ...................................................................................... 3-9
[4] Fixed Page (FIX) Area .............................................................................. 3-10
[5] Local Register Setting Area ...................................................................... 3-11
[6] ROM Window Setting Area ....................................................................... 3-11
3.1.4 Data Memory Access................................................................................ 3-12
[1] Byte Operation .......................................................................................... 3-12
[2] Word Operation ........................................................................................ 3-12
3.2
Registers...................................................................................................... 3-13
3.2.1 Arithmetic Register (ACC) ........................................................................ 3-13
3.2.2 Control Register ........................................................................................ 3-14
[1] Program Status Word (PSW).................................................................... 3-14
[2] Program Counter (PC).............................................................................. 3-17
[3] Local Register Base (LRB) ....................................................................... 3-17
[4] System Stack Pointer (SSP) ..................................................................... 3-18
3.2.3 Pointing Register (PR) .............................................................................. 3-19
3.2.4 Local Registers (R, ER) ............................................................................ 3-20
3.2.5 Segment Register ..................................................................................... 3-21
[1] Code Segment Register (CSR) ................................................................ 3-21
[2] Table Segment Register (TSR) ................................................................ 3-22
3.2.6 Special Function Register (SFR) .............................................................. 3-23
3.3
Addressing Mode ......................................................................................... 3-37
3.3.1 RAM Addressing ....................................................................................... 3-37
[1] Register Addressing ................................................................................. 3-37
[2] Page Addressing ...................................................................................... 3-40
[3] Direct Data Addressing ............................................................................. 3-43
[4] Pointing Register Indirect Addressing....................................................... 3-44
[5] Special Bit Area Addressing ..................................................................... 3-50
Contents-2
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