PEDL66517-03
1
Semiconductor
ML66517 Family
(2) External data memory control
(VDD = 4.5 to 5.5 V, Ta = –40 to +85°C)
Parameter
Cycle time
Symbol
tcyc
Condition
Min.
40
Max.
—
Unit
fOSC = 25 MHz
Clock pulse width (HIGH level)
Clock pulse width (LOW level)
ALE pulse width
tφWH
tφWL
tAW
13
—
13
—
2tφ – 10
2tφ – 18
2tφ – 18
tφ – 5
tφ – 5
2tφ – 15
tφ – 13
3tφ – 30
tφ – 3
30
—
RD pulse width
WR pulse width
tRW
—
tWW
tRAD
tWAD
tALS
tALH
tAHS
tAHH
tRS
—
RD pulse delay time
WR pulse delay time
Low address setup time
Low address hold time
High address setup time
High address hold time
Read data setup time
Read data hold time
Write data setup time
Write data hold time
—
—
ns
CL = 50 pF
—
—
—
—
—
tRH
0
tφ – 3
—
tWS
2tφ – 30
tφ – 3
tWH
—
Note: tφ = tcyc/2
tcyc
CPUCLK
tφWL
tφWH
tAW
ALE
RD
tRAD
tRW
AD0 to AD7
RAP0 to 7
DIN0 to 7
tRS
tRH
tALS
tALH
A8 to A15
RAP8 to 15
tAHH
tAHS
WR
tWAD
tWW
AD0 to AD7
A8 to A15
RAP0 to 7
DOUT0 to 7
tWH
tWS
tALS
tALH
RAP8 to 15
tAHH
tAHS
Bus timing during no wait cycle time
20/28
OKI [ OKI ELECTRONIC COMPONETS ]
