PEDL60851C-02
1
Semiconductor
ML60851C
Revision Register (REVISION)
Read address
Write address
CDh
—
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
After a bus reset
Definition
Revision No. of Chip
Transmit FIFO Clear Register (CLRFIFO)
Read address
Write address
—
4Eh
D7
0
D6
0
D5
D4
D3
D2
D1
D0
0
Cannot be read (indeterminate)
After a hardware reset
After a bus reset
Definition
Cannot be read (indeterminate)
0
EP1 Transmit FIFO Clear
EP2 Transmit FIFO Clear
EP3 Transmit FIFO Clear
EP1 to EP3 FIFO Clear: When each EP has been set for transmission, by writing a “1” in these bits, the
corresponding FIFOs are cleared at the Write pulse and also the corresponding EP
Packet Ready bits are reset.
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OKI [ OKI ELECTRONIC COMPONETS ]
