––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ ML53612 ■
6.6 Clock Skew Requirements
(Extract from H.100/H.110 Specifications, Rev. 1.0)
Parameter
Symbol
Min
Typ
Max
Unit
ns
Notes
[1] [2] [3] [4]
(H.100) Max Skew between CT_C8 "A" and "B" Tskc8
(H.110) Max Skew between CT_C8 "A" and "B" Tskc8
10
10
Φ
[2] [3] [4] [5]
[1]
Φ
ns
(H.100) Max Skew between CT_C8_A and any Tskcomp
compatibility clock
5
5
ns
[5]
(H.110) Max Skew between CT_C8_A and any Tskcomp
compatibility clock
ns
1. Test Load – 200 pF.
2. Assumes "A" and "B" masters in adjacent slots.
3. When static skew is 10nS and, in the same clock cycle, each clock performs a 10nS phase correction in opposite directions, a maximum skew of
30nS will occur during that clock cycle.
4. Meeting the skew requirements in Table 2 and the requirements of Section 2.3 (in the H.100/H.110 Specifications, Rev. 1.0) could require the
PLL’s generating CT_C8 to have different time constants when acting as primary and secondary clock masters.
5. Test Load - "A" load = "B" load.
Vt+
Vt+
CT_C8_A
CT_C8_B
CT_C8_A
Tskc8
Tskcomp
Tskcomp
Vt+
Vt+
Vt-
Inter-operability Clocks
Figure 15. Clock Skew Requirements
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