■ ML53612 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
17. Φ (Phase Correction) results from PLL timing corrections.
H.100. Measuring conditions:
Data lines
Vth (threshold voltage) = 1.4V
Vhi (test high voltage) = 2.4V
Vlo (test low voltage) = 0.4V
Input signal edge rate = 1 V/nS
Vt+ (test high voltage) = 2.0V
Vt- (test low) = 0.6V
Clock and Frame lines
Data lines
Input signal edge rate = 1 V/nS
Vhi (test high voltage) = 2.0V
Vlo (test low voltage) = 0.8V
Input signal edge rate = 1 V/nS
Vt+ (test high voltage) = 2.0V
Vt- (test low voltage) = 0.6V
Input signal edge rate = 1 V/nS
H.110. Measuring conditions:
Clock and Frame lines
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Oki Semiconductor