––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ ML53612 ■
6.5 H.100/H.110 Bus Timing Specification
(Extract from H.100/H.110 Specifications, Rev. 1.0)
Parameter
Clock edge rate (All Clocks)
Symbol
Min
0.25
0.25
Typ
Max
2
Unit
V/ns
V/ns
Notes
[1]
[1]
H.100
CT_C8_(A/B) and CT_FRAME_(A/B)_N H.110
edge rate
2
[2]
[3]
[4]
CT_NETREF edge rate
H.110
0.3
122.074+Φ
73+Φ
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock CT_C8_(A/B) Period
Clock CT_C8_(A/B) High Time
Tc8p
122.066-Φ
49-Φ
H.100
H.110
H.100
H.110
Tc8h
[4] [5]
63-Φ
69+Φ
[4]
Clock CT_C8_(A/B) Low Time
Tc8l
49-Φ
73+Φ
[4] [5]
63-Φ
69+Φ
[6]
Data Sample Point
Tsamp
Tdoz
90
[7] [8] [9]
[8] [9] [10]
[7] [8] [9]
[8] [9] [10]
[7] [8]
Data Output to HiZ Time
H.100
H.110
H.100
H.110
H.100
H.110
H.100
H.110
H.100
H.110
-20
-10
0
0
0
Data HiZ to Output Time
Data Output Delay Time
Data Valid Time
Tzdo
Tdod
Tdv
22
11
22
11
69
83
112
112
180
90
90
10
0
0
[8] [10]
[7] [11] [12]
[11] [13] [14]
0
0
0
Data Invalid Time
Tdiv
102
102
90
45
45
0
[15] [16]
CT_FRAME_(A/B)_N Width
CT_FRAME_(A/B)_N Setup Time
CT_FRAME_(A/B)_N Hold Time
Phase Correction
Tfp
Tfs
Tfh
Φ
122
[17]
1. The rise and fall times are determined by the edge rate in V/nS. A maximum edge rate is the fastest rate at which a clock transitions.
2. 10ꢀ - 90ꢀ. Test Load = 150 pF.
3. Tc8p Min and Max are under free-run conditions assuming 32 ppm clock accuracy.
4. Non-cumulative, Tc8p requirements still need to be met.
5. Duty Cycle measured at transmitter under no load conditions.
6. For reference only
7. Test Load - 200 pF
8. Measured at the transmitter.
9. Tdoz and Tzdo apply at every time-slot boundary.
10. Test Load - 12 pF
11. Measured at the receiver.
12. Reference only: Tdv = Max. clock cable delay + Max. data cable delay + Max. data HiZ to output time = 12nS + 35nS + 22 nS = 69nS. Max. clock
cable delay and max. data cable delay are worst case numbers based on electrical simulation.
13. Reference only: Tdv = Max. clock backplane delay + Max. data backplane delay + Max. data HiZ to output time = 26nS + 46nS + 11nS = 83nS. Max.
clock delay and max. data delay are worst case numbers based on electrical simulation.
14. Based on worst case electrical simulation.
15. This range accounts for Φ (Phase Correction).
16. Tcell = Max. clock backplane delay + Max. data backplane delay + Max. Tzdo + (Min. Tdiv - Max. Tdv) + Max Tdoz + F = 26nS + 46nS + 11nS +
(102nS - 83nS) + 10nS + 10nS = 122nS. Max. clock delay and max. data delay are worst case numbers based on electrical simulation.
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