■ ML53612 ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
6.4 AC Electrical Characteristics
Note: Signals ending in “_N” are active low.
[1] [2] [3]
Microprocessor Interface Timing - Intel Bus Mode, Non-multiplexed Address
Parameter
Symbol
Min
40
40
5
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS_N setup to WR_N ↑
t1
t2
t3
t4
t5
t6
t7
t8
t9
WR_N pulse width
A_[9:0] setup to WR_N ↓ (C_96=1)
A_[2:0] setup to WR_N ↑(C_96=0)
A_[9:0] hold from WR_N ↑
40
5
D_[7:0] setup to WR_N ↑
40
5
D_[7:0] hold from WR_N ↑
D_[7:0] float to valid delay from CS_N RD_N, and A_[9:0]
D_[7:0] valid to float delay from CS_N or RD_N
0
50
10
0
1. Timing measured with 100 pF load on D_[7:0].
2. Write cycle may be controlled by CS_N or WR_N.
3. ALE=1.
t1
CS_N
RD_N
t2
WR_N
t3
t4
t5
t7
A_[9:0]
t6
t8
t9
D_[7:0]
Figure 7. Microprocessor Interface Timing - Intel Bus Mode, Non-multiplexed Address
50
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