––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ ML53612 ■
[1] [2] [3]
Microprocessor Interface Timing - Motorola Bus Mode, Non-multiplexed Address
Parameter
Symbol
Min
40
40
5
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS_N setup to STRB_N ↑
STRB_N pulse width
t1
t2
t3
t4
t5
t6
t7
t8
t9
R/W_N setup to STRB_N ↓
R/W_N hold from STRB_N ↑
5
A_[9:0] setup to STRB_N ↓ (C_96=1)
A_[2:0] setup to STRB_N ↑ (C_96=0)
A_[9:0] hold from STRB_N ↑
5
40
5
D_[7:0] setup to STRB_N ↑
40
5
D_[7:0] hold from STRB_N ↑
D_[7:0] float to valid delay from CS_N, STRB_N, and A_[9:0]
D_[7:0] valid to float delay from CS_N or STRB_N
t10
t11
0
50
10
0
1. Timing measured with 100 pF load on D_[7:0].
2. Write cycle may be controlled by CS_N or STRB_N.
3. AS=1.
t1
CS_N
t2
STRB_N
t3
t4
t3
t4
R/W_N
t5
t6
t7
t9
A_[9:0]
D_[7:0]
t8
t10
t11
Figure 8. Microprocessor Interface Timing - Motorola Bus Mode, Non-multiplexed Address
Oki Semiconductor
51