■ MG113P/114P/115P/73P/74P/75P ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
More information on OKI’s floorplanning capabilities is available in Oki’s Application Note, Using Oki’s
Floorplanner: Standalone Operation and Links to Synopsys.
Incremental
Optimization with
Physical Information
Initial Synthesis
HDL Entry
No
Constraints Met?
PDEF
Yes
(Synopsis)
Constraints
Synthesis
Invoke Import on
Floorplanner
Gate Level
Netlist
No
Constraints Met?
Yes
Gate Level
Netlist
(EDIF)
(EDIF)
Incremental
Floorplan
Initial Floorplan
DSPF/Oki RC/
PDEF (Synopsys)
Wire Load Model (Synopsys)
Net Capacitance (Synopsys
Script (Synopsys)
Invoke Export on
Floorplanner
Invoke Delay
Delay
(SDF)
Load
Back-Annotation Files
No
Constraints Met?
Yes
= In Synopsys DC/DA
= In Floorplanner
Timing Optimization
To Simulation and P&R
Figure 14. LSF System Design Flow
IEEE JTAG Boundary Scan Support
Boundary scan offers efficient board-level and chip-level testing capabilities. Benefits resulting from
incorporating boundary-scan logic into a design include:
• Improved chip-level and board-level testing and failure diagnostic capabilities
• Support for testing of components with limited probe access
• Easy-to-maintain testability and system self-test capability with on-board software
• Capability to fully isolate and test components on the scan path
• Built-in test logic that can be activated and monitored
• An optional Boundary Scan Identification (ID) Register
16
Oki Semiconductor
OKI [ OKI ELECTRONIC COMPONETS ]
