■ MG113P/114P/115P/73P/74P/75P ■ ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
Design Process
The following figure illustrates the overall IC design process, also indicating the three main interface
points between external design houses and Oki ASIC Application Engineering.
[5]
Level 1
VHDL/HDL Description
Synthesis
Test Vectors
CAE Front-End
[2]
LSF
Floorplanning
Gate-Level Simulation
Level 2
Netlist Conversion
(EDIF 200)
Test Vector Conversion
[4]
(Oki TPL
)
Scan Insertion (Optional)
[3]
TDC
[1]
CDC
Pre-Layout Simulation
(Cadence Verilog)
Floorplanning
Layout
[5]
Level 2.5
Oki Interface
[6]
Fault Simulation
Automatic Test
Pattern Generation
(Synopsys Test Compiler)
Verification
(Cadence DRACULA)
Post-Layout Simulation
(Cadence Verilog)
[5]
Level 3
Manufacturing
Prototype
Test Program
Conversion
[1] Oki’s Circuit Data Check program (CDC) verifies logic design rules
[2] Oki’s Link to Synthesis Floorplanning toolset (LSF) transfers post-floorplanning timing for resynthesis
[3] Oki’s Test Data Check program (TDC) verifies test vector rules
[4] Oki’s Test Pattern Language (TPL)
[5] Alternate Customer-Oki design interfaces available in addition to standard level 2
[6] Standard design process includes fault simulation
Figure 12. Oki’s Design Process
14
Oki Semiconductor
OKI [ OKI ELECTRONIC COMPONETS ]
