––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ MG113P/114P/115P/73P/74P/75P ■
Automatic Test Pattern Generation
Oki’s 0.25µm ASIC technologies support ATPG using full scan-path design techniques, including the fol-
lowing:
• Increases fault coverage ≥ 95%
• Uses Synopsys Test Compiler
• Automatically inserts scan structures
• Connects scan chains
• Traces and reports scan chains
• Checks for rule violations
• Generates complete fault reports
• Allows multiple scan chains
• Supports vector compaction
ATPG methodology is described in detail in Oki’s 0.25µm Scan Path Application Note.
Combinational Logic
A
B
FD1AS
FD1AS
D
Q
D
Q
Scan Data Out
C
C
Scan Data In
Scan Select
SD
SS
SD
SS
QN
QN
Figure 13. Full Scan Path Configuration
Floorplanning Design Flow
Oki offers two floorplanning tools for high-density ASIC design: Cadence DP3, and Gambit GFP. The
two main purposes for Oki’s floorplanning tools are to:
• Ensure conformance of critical circuit performance specifications
• Shorten overall design TAT
In a traditional design approach with synthesis tools, timing violations after prelayout simulation are
fixed by manual editing of the netlist. This process is difficult and time consuming. Also, there is no
physical cluster information provided in the synthesis tool, and so it is difficult to synthesize logic using
predicted interconnection delay due to wire length. Synthesis tools may therefore create over-optimized
results.
To minimize these problems, Synopsys proposed a methodology called, “Links to Layout (LTL)”. Based
on this methodology, Oki developed an interface between Oki’s Floorplanner and the Synopsys environ-
ment, called Link Synopsys to Floorplanner (LSF). As not every Synopsys user has access to the Synopsys
Floorplan Management tool, Oki had developed the LSF system to support both users who can access
Synopsys Floorplan Management and users who do not have access to Synopsys Floorplan Manage-
ment.
Oki Semiconductor
15
OKI [ OKI ELECTRONIC COMPONETS ]
