Philips Semiconductors
Product specification
Economy Autosync Deflection Controller
(EASDC)
SYMBOL
PARAMETER
CONDITIONS
MIN.
−0.7
4.4
−
−
0.3
TYP.
−1.0
4.8
300
−
−
TDA4858
MAX.
−1.35
5.2
−
UNIT
V
ERTICAL SYNC OUTPUT AT
VSYNC (
PIN
14)
DURING COMPOSITE SYNC AT
HSYNC (
PIN
15)
I
VSYNC
V
VSYNC
output current
internal clamping voltage level
steepness of slopes
Automatic polarity correction for vertical sync
t
VSYNC(max)
t
d(VPOL)
t
clamp(CLBL)
V
clamp(CLBL)
TC
clamp
maximum width of vertical sync
pulse
delay for changing polarity
300
1.8
µs
ms
µs
V
mV/K
ns/V
V
µs
mV/K
V
mV/K
mA
mA
during internal vertical
sync
during internal vertical
sync
mA
V
ns/mA
Video clamping/vertical blanking output [CLBL (pin 16)]
width of video clamping pulse
top voltage level of video
clamping pulse
temperature coefficient of
V
clamp(CLBL)
steepness of slopes for
clamping pulse
V
blank(CLBL)
t
blank(CLBL)
TC
blank
V
scan(CLBL)
TC
scan
I
sink(CLBL)
I
load(CLBL)
V
CLSEL
top voltage level of vertical
blanking pulse
width of vertical blanking pulse
temperature coefficient of
V
blank(CLBL)
output voltage during vertical
scan
temperature coefficient of
V
scan(CLBL)
internal sink current
external load current
I
CLBL
= 0
R
L
= 1 MΩ; C
L
= 20 pF
note 1
measured at V
CLBL
= 3 V
0.6
4.32
−
−
1.7
240
−
0.59
−
2.4
−
7
0.7
4.75
+4
50
1.9
300
+2
0.63
−2
−
−
−
0.8
5.23
−
−
2.1
360
−
0.67
−
−
−3.0
V
CC
S
ELECTION OF LEADING
/
TRAILING EDGE TRIGGER FOR VIDEO CLAMPING PULSE
voltage at CLSEL (pin 10) for
trigger with leading edge of
horizontal sync
voltage at CLSEL for trigger
with trailing edge of horizontal
sync
t
d(clamp)
delay between leading edge of
horizontal sync and start of
horizontal clamping pulse
delay between trailing edge of
horizontal sync and start of
horizontal clamping pulse
V
CLSEL
> 7 V
V
0
−
5
V
−
300
−
ns
V
CLSEL
< 5 V
−
130
−
ns
1997 Oct 27
14
PHILIPS [ NXP SEMICONDUCTORS ]
