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P5CD081 参数 Datasheet PDF下载

P5CD081图片预览
型号: P5CD081
PDF下载: 下载PDF文件 查看货源
内容描述: 安全双接口,并联系PKI智能卡控制器 [Secure dual interface and contact PKI smart card controller]
分类和应用: 控制器
文件页数/大小: 20 页 / 151 K
品牌: NXP [ NXP ]
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P5CD016/021/041/051 and P5Cx081  
NXP Semiconductors  
Secure dual interface and contact PKI smart card controller  
„ Typical EEPROM page erasing time: 1.7 ms  
„ Typical EEPROM page programming time: 1.0 ms  
„ Power-saving Idle mode  
„ Wake-up from Idle mode by RESET or any activated interrupt  
„ Contact configuration and serial interface in accordance with ISO/IEC 7816  
„ Power-saving Sleep (power-down) mode or Clockstop mode  
„ ISO/IEC 7816 UART supporting standard protocols T=0 and T=1 as well as high  
speed personalization up to 1 Mbit/s  
„ External or internally generated configurable CPU clock  
„ 1 MHz to 10 MHz operating external clock frequency range  
‹ Internal CPU clock up to 62 MHz with synchronous operation  
‹ Internal clocking independent of externally applied frequency  
„ High speed 16-bit CRC engine in accordance with ITU-T polynomial definition  
„ Low power Random Number Generator (RNG) in hardware, AIS-31 compliant  
„ 1.62 V to 5.5 V extended operating voltage range for class C, B and A  
„ Optional extended Class B operation mode (2.2 V to 5.5 V targeted for battery  
supplied applications)  
„ 25 °C to +85 °C ambient temperature  
„ Broad spectrum of delivery types:  
‹ Wafers  
‹ Modules  
‹ Packages  
‹ Inlays  
2.2 Product specific family features  
„ P5CC081  
‹ ISO/IEC 7816 contact interface  
‹ Two additional I/O ports: IO2 and IO3 for full-duplex serial data communication  
„ P5CD016, P5CD021, P5CD041, P5CD051 and P5CD081  
‹ CIU fully compatible with ISO/IEC 14443A:  
- 13.56 MHz operating frequency  
- fully supports the T=CL protocol in accordance with ISO/IEC 14443-4  
- factory configurable for higher input capacitance to match smaller loop antennas  
- supported data transfer rates: 106 kbit/s, 212 kbit/s, 424 kbit/s and 848 kbit/s  
- MIFARE reader infrastructure compatibility via optional MIFARE 1 K or 4 K  
implementation including built-in anticollision support  
‹ Two additional I/O ports: IO2 and IO3 for full-duplex serial data communication  
„ P5CN081  
‹ S2C interface  
‹ One additional I/O port: IO2 for optional proprietary use  
P5CD016_021_041_51_Cx081_FAM_SDS  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product short data sheet  
PUBLIC  
Rev. 3.2 — 14 March 2011  
150332  
7 of 20  
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