NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
VIN
SW2IN
SW2MODE
I
SENSE
C
INSW2
CONTROLLER
SW2
SW2LX
EP
DRIVER
L
SW2
SW2FAULT
C
OSW2
2
I C
INTERFACE
INTERNAL
COMPENSATION
I2C
Z2
SW2FB
Z1
EA
V
DAC
REF
aaa-026486
Figure 17.ꢀSW2 block diagram
10.4.4.4.1 SW2 setup and control registers
SW2 output voltage is programmable from 0.400 V to 3.300 V; however, bit SW2[6] in
register SW2VOLT is read-only during normal operation. Its value is determined by the
default configuration, or may be changed by using the OTP registers. Therefore, once
SW2[6] is set to 0, the output is limited to the lower output voltage range from 0.400 V
to 1.975 V with 25 mV increments, as determined by bits SW2[5:0]. Likewise, once bit
SW2[6] is set to 1, the output voltage is limited to the higher output voltage range from
0.800 V to 3.300 V with 50 mV increments, as determined by bits SW2[5:0].
In order to optimize the performance of the regulator, it is recommended only voltage
from 2.000 V to 3.300 V be used in the high range, and the lower range be used for
voltage from 0.400 V to 1.975 V.
The output voltage set point is independently programmed for normal, standby, and
sleep mode by setting the SW2[5:0], SW2STBY[5:0] and SW2OFF[5:0] bits, respectively.
However, the initial state of bit SW2[6] are copied into bits SW2STBY[6], and SW2OFF[6]
bits. Therefore, the output voltage range remains the same in all three operating modes.
Table 53 shows the output voltage coding valid for SW2.
Note: Voltage set points of 0.6 V and below are not supported.
Table 53.ꢀSW2 output voltage configuration
Low output voltage range [1]
High output voltage range
Set point
SW2[6:0]
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
SW2 output
0.4000
0.4250
0.4500
0.4750
0.5000
0.5250
0.5500
0.5750
0.6000
Set point
SW2[6:0]
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
SW2 output
0.8000
0.8500
0.9000
0.9500
1.0000
1.0500
1.1000
1.1500
1.2000
0
1
2
3
4
5
6
7
8
64
65
66
67
68
69
70
71
72
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
54 / 137
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