NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
12.6 Thermal information
12.6.1 Rating data
The thermal rating data of the packages has been simulated with the results listed in
Table 4.
Junction to Ambient Thermal Resistance Nomenclature: the JEDEC specification
reserves the symbol RθJA or θJA (Theta-JA) strictly for junction-to-ambient thermal
resistance on a 1s test board in natural convection environment. RθJMA or θJMA (Theta-
JMA) is used for both junction-to-ambient on a 2s2p test board in natural convection
and for junction-to-ambient with forced convection on both 1s and 2s2p test boards. It is
anticipated that the generic name, Theta-JA, continues to be commonly used.
The JEDEC standards can be consulted at http://www.jedec.org/.
12.6.2 Estimation of junction temperature
An estimation of the chip junction temperature TJ can be obtained from the equation:
TJ = TA + (RθJA x PD) with
TA = Ambient temperature for the package in °C
RθJA = Junction to ambient thermal resistance in °C/W
PD = Power dissipation in the package in W
The junction-to-ambient thermal resistance is an industry standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in
common usage:
• The value determined on a single layer board RθJA
• The value obtained on a four layer board RθJMA
Actual application PCBs show a performance close to the simulated four layer board
value. This performance may be somewhat degraded in case of significant power
dissipated by other components placed close to the device.
At a known board temperature, the junction temperature TJ is estimated using the
following equation TJ = TB + (RθJB x PD) with
TB = Board temperature at the package perimeter in °C
RθJB = Junction to board thermal resistance in °C/W
PD = Power dissipation in the package in W
When the heat loss from the package case to the air can be ignored, acceptable
predictions of junction temperature can be made. See Section 10 "Functional block
requirements and behaviors" for more details on thermal management.
13 Packaging
Table 139.ꢀPackage drawing information
Package
Suffix
ES
Package outline drawing number
56 QFN 8x8 mm - 0.5 mm pitch.
WF-type (wettable flank)
98ASA00589D
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
130 / 137
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