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MC34PF4210A0ES 参数 Datasheet PDF下载

MC34PF4210A0ES图片预览
型号: MC34PF4210A0ES
PDF下载: 下载PDF文件 查看货源
内容描述: [14-channel power management integrated circuit (PMIC) for audio/video applications]
分类和应用: 集成电源管理电路
文件页数/大小: 137 页 / 1328 K
品牌: NXP [ NXP ]
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NXP Semiconductors  
PF4210  
14-channel power management integrated circuit (PMIC) for audio/video applications  
12.2 Component placement  
It is desirable to keep all components related to the power stage as close to the PMIC as  
possible, especially decoupling input and output capacitors.  
12.3 General routing requirements  
Some recommended things to keep in mind for manufacturability:  
Via in pads require a 4.5 mil minimum annular ring. Each pad must be 9.0 mils larger  
than its hole  
Maximum copper thickness for lines less than 5.0 mils wide is 0.6 oz copper  
Minimum allowed spacing between line and hole pad is 3.5 mils  
Minimum allowed spacing between line and line is 3.0 mils  
Care must be taken with SWxFB pins traces. These signals are susceptible to noise  
and must be routed far away from power, clock, or high-power signals, like the ones on  
the SWxIN, SWx, SWxLX, SWBSTIN, SWBST, and SWBSTLX pins. They could also  
be shielded.  
Shield feedback traces of the regulators and keep them as short as possible (trace  
them on the bottom so the ground and power planes shield these traces).  
Avoid coupling traces between important signal/low-noise supplies (like REFCORE,  
VCORE, VCOREDIG) from any switching node (for example, SW1ALX, SW1BLX,  
SW1CLX, SW2LX, SW3ALX, SW3BLX, SW4LX, and SWBSTLX).  
Make sure that all components related to a specific block are referenced to the  
corresponding ground.  
12.4 Parallel routing requirements  
I2C signal routing  
CLK is the fastest signal of the system, therefore it must be given special care.  
To avoid contamination of these delicate signals by nearby high-power or high-  
frequency signals, it is a good practice to shield them with ground planes placed on  
adjacent layers. Make sure the ground plane is uniform throughout the entire signal  
trace length.  
DO  
Signal  
DON'T  
Signal  
Ground plane  
Ground planes  
aaa-023891  
These signals can be placed on an outer layer of the board to reduce their  
capacitance with respect to the ground plane.  
Care must be taken with these signals not to contaminate analog signals, as they are  
high-frequency signals. Another good practice is to trace them perpendicularly on  
different layers, so there is a minimum area of proximity between signals.  
PF4210  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2018. All rights reserved.  
Data sheet: technical data  
Rev. 2.0 — 14 November 2018  
128 / 137  
 
 
 
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