LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
13.2 Standard I/O pin configuration
Figure 45 shows the possible pin modes for standard I/O pins:
• Digital output driver: enabled/disabled.
• Digital input: Pull-up enabled/disabled.
• Digital input: Pull-down enabled/disabled.
• Digital input: Repeater mode enabled/disabled.
• Z mode; High impedance (no cross-bar currents for floating inputs).
For initial device revision 0A (Boot ROM version 21.0), the default configuration for the
standard I/O pins is PU mode (input mode, pull-up enabled, pull-up resistor pulls up pin to
VDD). For future device revision 1B (Boot ROM version 21.1), the default configuration for
the standard I/O pins is Z mode (high impedance; pull-up or pull-down disabled). See the
Errata sheet LPC540xx (IOCON.1) for more details. The weak MOS devices provide a
drive capability equivalent to pull-up and pull-down resistors. For future device revision 1B
(Boot ROM version 21.1), GPIO pins PIO0_12, PIO0_11, PIO0_2, PIO0_3, PIO0_4,
PIO0_5, and PIO0_6 have the input buffer enabled (DIGIMODE, bit 8 is enabled in
IOCON register) and will be floating by default. If unused, it is recommended to externally
terminate this pins to prevent leakage.
VDD
ESD
enable output driver
data output from core
PIN
slew rate bit SLEW
input buffer enable bit EZI
data input to core
GLITCH
FILTER
filter select bit ZIF
ESD
VSS
pull-up enable bit EPUN
pull-down enable bit EPD
analog I/O
aaa-015595
The glitch filter rejects pulses of typical 12 ns width.
Fig 45. Standard I/O and RESET pin configuration
LPC540xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
145 of 168
NXP [ NXP ]
