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LPC54018JBD208 参数 Datasheet PDF下载

LPC54018JBD208图片预览
型号: LPC54018JBD208
PDF下载: 下载PDF文件 查看货源
内容描述: [32-bit ARM Cortex-M4 microcontroller]
分类和应用:
文件页数/大小: 168 页 / 3551 K
品牌: NXP [ NXP ]
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LPC540xx  
NXP Semiconductors  
32-bit ARM Cortex-M4 microcontroller  
Table 53. ADC sampling times[1] …continued  
-40 C Tamb <= 85 C; 1.71 V VDDA 3.6 V; 1.71 V VDD 3.6 V  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 10 bit  
[3]  
[3]  
[3]  
ts  
sampling time  
Zo < 0.05 kΩ  
35  
38  
40  
46  
61  
86  
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
0.05 k<= Zo < 0.1 kΩ  
0.1 k<= Zo < 0.2 kΩ  
0.2 k<= Zo < 0.5 kΩ  
0.5 k<= Zo < 1 kΩ  
1 k<= Zo < 5 kΩ  
ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 8 bit  
ts  
sampling time  
Zo < 0.05 kΩ  
27  
29  
32  
36  
48  
69  
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
0.05 k<= Zo < 0.1 kΩ  
0.1 k<= Zo < 0.2 kΩ  
0.2 k<= Zo < 0.5 kΩ  
0.5 k<= Zo < 1 kΩ  
1 k<= Zo < 5 kΩ  
ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 6 bit  
ts  
sampling time  
Zo < 0.05 kΩ  
20  
22  
23  
26  
36  
51  
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
0.05 k<= Zo < 0.1 kΩ  
0.1 k<= Zo < 0.2 kΩ  
0.2 k<= Zo < 0.5 kΩ  
0.5 k<= Zo < 1 kΩ  
1 k<= Zo < 5 kΩ  
[1] Characterized through simulation. Not tested in production.  
[2] The ADC default sampling time is 2.5 ADC clock cycles. To match a given analog source output  
impedance, the sampling time can be extended by adding up to seven ADC clock cycles for a maximum  
sampling time of 9.5 ADC clock cycles. See the TSAMP bits in the ADC CTRL register.  
[3] Zo = analog source output impedance.  
[4] For VDD 2.5 V, add one additional clock cycle to the values in Table 53.  
12.2.1 ADC input impedance  
Figure 42 shows the ADC input impedance. In this figure:  
ADCx represents slow ADC input channels 6 to 11.  
ADCy represents fast ADC input channels 0 to 5.  
R1 and Rsw are the switch-on resistance on the ADC input channel.  
If fast channels (ADC inputs 0 to 5) are selected, the ADC input signal goes through  
R
sw to the sampling capacitor (Cia).  
If slow channels (ADC inputs 6 to 11) are selected, the ADC input signal goes through  
R1 + Rsw to the sampling capacitor (Cia).  
Typical values, R1 = 487 , Rsw = 278   
See Table 20 for Cio.  
See Table 52 for Cia.  
LPC540xx  
All information provided in this document is subject to legal disclaimers.  
© NXP Semiconductors N.V. 2018. All rights reserved.  
Product data sheet  
Rev. 1.8 — 22 June 2018  
141 of 168  
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