LPC540xx
NXP Semiconductors
32-bit ARM Cortex-M4 microcontroller
3.3 V
3.3 V
3.3 V
SWD connector
(4)
(6)
SWDIO/PIO0_12
~10 kΩ - 100 kΩ
XTALIN
C1
(1)
1
2
C2
XTALOUT
RTCXIN
DGND
~10 kΩ - 100 kΩ
SWCLK/PIO0_11
(6)
3
4
n.c.
n.c.
C3
(1)
6
8
5
7
9
C4
n.c.
RTCXOUT
DGND
RESETN
10
V
SS
(2)
V
DD
3.3 V
0.1 ꢀF
0.01 ꢀF
DGND
DGND
V
SSA
DGND
LPC
AGND
PIO0_4
(3)
V
DDA
3.3 V
0.1 ꢀF
10 ꢀF
PIO0_5
PIO0_6
ISP select pins
(5)
DGND
(3)
VREFP
ADCx
3.3 V
0.1 ꢀF
10 ꢀF
0.1 ꢀF
VREFN
AGND
AGND
(7)
VBAT
3.3 V
0.1 ꢀF
DGND
AGND
DGND
aaa-029082
(1) See Section 13.6 “XTAL oscillator” for the values of C1, C2, C3, and C4.
(2) Position the decoupling capacitors of 0.1 μF and 0.01 μF as close as possible to the VDD pin. Add one set of decoupling
capacitors to each VDD pin.
(3) Position the decoupling capacitors of 0.1 μF as close as possible to the VREFN and VDDA pins. The 10 μF bypass capacitor
filters the power line. Tie VDDA and VREFP to VDD if the ADC is not used. Tie VREFN to VSS if ADC is not used.
(4) Uses the ARM 10-pin interface for SWD.
(5) When measuring signals of low frequency, use a low-pass filter to remove noise and to improve ADC performance. Also see
Ref. 3.
(6) External pull-up resistors on SWDIO and SWCLK pins are optional because these pins have an internal pull-up enabled by
default on initial device revision 0A (Boot ROM version 21.0). For future device revision 1B (Boot ROM version 21.1), these pins
are in high Z mode (internal pull-up and pull-down disabled). See the Errata sheet LPC540xx (IOCON.1) for more details. For
future device revision 1B (Boot ROM version 21.1), GPIO pins SWDIO/PIO0_12, SWCLK/PIO0_11, PIO0_2, PIO0_3, PIO0_4,
PIO0_5, and PIO0_6 have the input buffer enabled (DIGIMODE, bit 8 is enabled in IOCON register) and will be floating by
default. If unused, it is recommended to externally terminate this pins to prevent leakage.
(7) Position the decoupling capacitor of 0.1 F as close as possible to the VBAT pin. Tie VBAT to VDD if not used.
Fig 46. Power, clock, and debug connections
LPC540xx
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 1.8 — 22 June 2018
147 of 168
NXP [ NXP ]
