NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
Table 4.
Symbol
Pin description
…continued
Pin
K1
J1
J2
J3
J4
U14
T13
R12
P12
R5
U3
L2
T3
T4
U13
R11
T12
V15
U4
R7
T5
U5
V3
V4
T6
R8
V5
U6
V6
T7
U7
V7
T8
U8
Power supply
domain
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
VDD_EMC
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
I
O
O
O
O
I/O: BK
I/O: BK
I/O: BK
I/O: BK
I/O: BK
I/O: BK
I/O: BK
I/O: BK
I/O: BK
I/O: BK
I/O: BK
I/O: BK
I/O: BK
I/O: BK
I/O: BK
I/O: BK
Description
EMC address bit 19
Port 1 GPIO bit 19
EMC address bit 20
Port 1 GPIO bit 20
EMC address bit 21
Port 1 GPIO bit 21
EMC address bit 22
Port 1 GPIO bit 22
EMC address bit 23
Port 1 GPIO bit 23
Static memory byte lane 0 select
Static memory byte lane 1 select
Static memory byte lane 2 select
Static memory byte lane 3 select
SDRAM column address strobe out, active LOW
Clock enable out for SDRAM bank 0
Clock enable out for SDRAM bank 1
SDRAM clock out
SDRAM clock feedback
EMC static memory chip select 0
EMC static memory chip select 1
EMC static memory chip select 2
EMC static memory chip select 3
EMC data bit 0
EMC data bit 1
EMC data bit 2
EMC data bit 3
EMC data bit 4
EMC data bit 5
EMC data bit 6
EMC data bit 7
EMC data bit 8
EMC data bit 9
EMC data bit 10
EMC data bit 11
EMC data bit 12
EMC data bit 13
EMC data bit 14
EMC data bit 15
EMC_A[19]/P1[19]
EMC_A[20]/P1[20]
EMC_A[21]/P1[21]
EMC_A[22]/P1[22]
EMC_A[23]/P1[23]
EMC_BLS[0]
EMC_BLS[1]
EMC_BLS[2]
EMC_BLS[3]
EMC_CAS
EMC_CKE0
EMC_CKE1
EMC_CLK
EMC_CLKIN
EMC_CS0
EMC_CS1
EMC_CS2
EMC_CS3
EMC_D[0]
EMC_D[1]
EMC_D[2]
EMC_D[3]
EMC_D[4]
EMC_D[5]
EMC_D[6]
EMC_D[7]
EMC_D[8]
EMC_D[9]
EMC_D[10]
EMC_D[11]
EMC_D[12]
EMC_D[13]
EMC_D[14]
EMC_D[15]
LPC3220_30_40_50_1
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 01 — 6 February 2009
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