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LPC2368FBD100 参数 Datasheet PDF下载

LPC2368FBD100图片预览
型号: LPC2368FBD100
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片16位/ 32位微控制器;高达512 KB的闪存, ISP / IAP ,以太网, USB 2.0 ,CAN和10位ADC / DAC [Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC]
分类和应用: 闪存微控制器以太网
文件页数/大小: 48 页 / 1084 K
品牌: PHILIPS [ NXP SEMICONDUCTORS ]
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Philips Semiconductors
LPC2364/2366/2368
Fast communication chip
6. Pinning information
6.1 Pinning
100
76
75
51
26
50
002aac576
1
LPC2364FBD100
LPC2366FBD100
LPC2368FBD100
25
Fig 2. LPC2364/66/68 pinning
6.2 Pin description
Table 3.
Symbol
P0.0 to P0.31
Pin description
Pin
Type
location
I/O
Description
Port 0:
Port 0 is a 32 bit I/O port with individual direction controls for each bit. The
operation of port 0 pins depends upon the pin function selected via the Pin Connect
block. Pins 12, 13, 14, and 31 of this port are not available.
P0.0 —
General purpose digital input/output pin.
RD1 —
CAN1 receiver input.
TXD3 —
Transmitter output for UART3.
SDA1 —
I
2
C1 data input/output (this is not an open drain pin).
P0.1 —
General purpose digital input/output pin.
TD1 —
CAN1 transmitter output.
RXD3 —
Receiver input for UART3.
SCL1 —
I
2
C1 clock input/output (this is not an open drain pin).
P0.2 —
General purpose digital input/output pin.
TXD0 —
Transmitter output for UART0.
P0.3 —
General purpose digital input/output pin.
RXD0 —
Receiver input for UART0.
P0.4 —
General purpose digital input/output pin.
I2SRX_CLK —
Receive Clock. It is driven by the master and received by the slave.
Corresponds to the signal SCK in the I
2
S-bus specification.
RD2 —
CAN2 receiver input.
CAP2.0 —
Capture input for Timer 2, channel 0.
P0.0/RD1/
TXD3/SDA1
46
I/O
I
O
I/O
P0.1/TD1/
RXD3/SCL1
47
I/O
O
I
I/O
P0.2/TXD0
P0.3/RXD0
P0.4/
I2SRX_CLK/
RD2/CAP2.0
98
99
81
I/O
O
I/O
I
I/O
I/O
I
I
LPC2364_66_68_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 — 22 September 2006
5 of 48