LPC2210/2220
NXP Semiconductors
16/32-bit ARM microcontrollers
Table 14. External memory interface dynamic characteristics
CL = 25 pF; Tamb = 40 °C.
Symbol
Parameter
Conditions
Min
Typ Max
Unit
Common to read and write cycles
tCHAV
XCLK HIGH to address valid
time
-
-
10
ns
tCHCSL
tCHCSH
XCLK HIGH to CS LOW time
-
-
-
-
10
10
ns
ns
XCLK HIGH to CS HIGH
time
tCHANV
XCLK HIGH to address
invalid time
-
-
10
ns
Read cycle parameters
tCSLAV CS LOW to address valid
[1]
[1]
−5
−5
−5
-
-
+10
+10
ns
ns
time
tOELAV
OE LOW to address valid
time
tCSLOEL
tam
CS LOW to OE LOW time
memory access time
-
-
+5
-
ns
ns
[2][3]
[4]
(Tcy(CCLK) × (2 + WST1)) +
(−20)
[2][3]
[4]
tam(ibr)
tam(sbr)
memory access time (initial
burst-ROM)
(Tcy(CCLK) × (2 + WST1)) +
(−20)
-
-
-
-
ns
ns
[2][5]
memory access time
Tcy(CCLK) + (−20)
(subsequent burst-ROM)
[6]
th(D)
data hold time
0
-
-
-
-
ns
ns
ns
tCSHOEH
tOEHANV
CS HIGH to OE HIGH time
−5
−5
+5
+5
OE HIGH to address invalid
time
tCHOEL
tCHOEH
XCLK HIGH to OE LOW time
−5
−5
-
-
+5
+5
ns
ns
XCLK HIGH to OE HIGH
time
Write cycle parameters
[1]
tAVCSL
address valid to CS LOW
T
cy(CCLK) − 10
-
-
ns
time
tCSLDV
CS LOW to data valid time
CS LOW to WE LOW time
CS LOW to BLS LOW time
WE LOW to data valid time
CS LOW to data valid time
WE LOW to WE HIGH time
−5
−5
−5
−5
−5
-
-
-
-
-
-
+5
ns
ns
ns
ns
ns
ns
tCSLWEL
tCSLBLSL
tWELDV
tCSLDV
+5
+5
+5
+5
[2][4]
[2][4]
[2]
tWELWEH
T
T
T
cy(CCLK) × (1 + WST2) − 5
cy(CCLK) × (1 + WST2) − 5
cy(CCLK) − 5
Tcy(CCLK) ×
(1 + WST2) + 5
tBLSLBLSH BLS LOW to BLS HIGH time
-
-
Tcy(CCLK)
(1 + WST2) + 5
×
ns
ns
tWEHANV
tWEHDNV
WE HIGH to address invalid
time
Tcy(CCLK) + 5
[2]
[2]
WE HIGH to data invalid time
(2 × Tcy(CCLK)) − 5
Tcy(CCLK) − 5
-
-
(2 × Tcy(CCLK)) + 5 ns
Tcy(CCLK) + 5 ns
tBLSHANV BLS HIGH to address invalid
time
LPC2210_2220_6
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 06 — 11 December 2008
38 of 50
NXP [ NXP ]
