NXP Semiconductors
HEF4104B
Quad low-to-high voltage translator with 3-state outputs
V
I
negative
pulse
0V
t
W
90 %
V
M
10 %
t
f
t
r
t
r
t
f
90 %
V
M
10 %
t
W
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V
M
V
I
positive
pulse
0V
V
M
a. Input waveforms
V
EXT
V
DD
V
I
V
O
RL
G
RT
DUT
CL
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b. Test circuit
Test data given in
Definitions for test circuit:
DUT = Device Under Test.
C
L
= load capacitance including jig and probe capacitance.
R
L
= load resistance.
R
T
= termination resistance should be equal to the output impedance Z
o
of the pulse generator.
Fig 7.
Table 10.
Supplies
Test circuit for measuring switching times
Test data
Input
t
r
, t
f
≤
20 ns
Load
R
L
1 kΩ
C
L
50 pF
V
EXT
t
PHL
, t
PLH
open
t
PZL
, t
PLZ
V
DD(B)
t
PZH
, t
PHZ
V
SS
V
DD(A)
= V
DD(B)
5 V to 15 V
HEF4104B_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 16 December 2009
9 of 14
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