NXP Semiconductors
HEF4027B
Dual JK flip-flop
V
I
SD INPUT
0V
V
M
t
W
V
I
CD INPUT
0V
t
rec
V
I
CP INPUT
0V
V
M
V
M
t
W
t
rec
V
OH
Q OUTPUT
V
OL
001aae597
V
OH
and V
OL
are typical output voltages levels that occur with the output load.
Measurement points are given in
Fig 6.
Table 9.
V
DD
Waveforms showing pulse widths and recovery times
Measurement points
Input
V
M
0.5V
DD
Output
V
M
0.5V
DD
Supply voltage
5 V to 15 V
V
DD
V
I
G
RT
V
O
DUT
CL
001aag182
Test data is given in
Definitions for test circuit:
DUT = Device Under Test.
C
L
= load capacitance including jig and probe capacitance.
R
T
= termination resistance should be equal to the output impedance Z
o
of the pulse generator.
Fig 7.
Table 10.
V
DD
Test circuit
Test data
Input
V
I
V
SS
or V
DD
t
r
, t
f
≤
20 ns
Load
C
L
50 pF
Supply voltage
5 V to 15 V
HEF4027B_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 10 November 2008
8 of 13
PHILIPS [ NXP SEMICONDUCTORS ]
