NXP Semiconductors
HEF4027B
Dual JK flip-flop
6. Pinning information
6.1 Pinning
HEF4027B
2Q
2Q
2CP
2CD
2K
2J
2SD
V
SS
1
2
3
4
5
6
7
8
001aae594
16 V
DD
15 1Q
14 1Q
13 1CP
12 1CD
11 1K
10 1J
9
1SD
Fig 3.
Pin configuration
6.2 Pin description
Table 2.
Symbol
V
SS
1SD, 2SD
1J, 2J
1K, 2K
1CD, 2CD
1CP, 2CP
1Q, 2Q
1Q, 2Q
V
DD
Pin description
Pin
8
9, 7
10, 6
11, 5
12, 4
13, 3
14, 2
15, 1
16
Description
ground supply voltage
asynchronous set-direct input (active HIGH)
synchronous input
synchronous input
asynchronous clear-direct input (active HIGH)
clock input (LOW-to-HIGH edge-triggered)
complement output
true output
supply voltage
7. Functional description
Table 3.
Inputs
nSD
H
L
H
nCD
L
H
H
nCP
X
X
X
nJ
X
X
X
nK
X
X
X
Function table
Outputs
nQ
H
L
H
nQ
L
H
H
HEF4027B_5
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 10 November 2008
3 of 13
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