NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
PTBPE[1:0]
PTBDD[1:0]
KBIPE[3:0]
KBEDG[3:0]
Pullup
Pulldown
(pull enable)
(data direction)
(KBI pin enable)
(KBI Edge Select)
0
1
x
0
0
1
x
x
x
x
x
x
disabled
enabled
disabled
x
x
x
The data direction control bit (PTxDDn) determines whether the output buffer for the
associated pin is enabled, and also controls the source for port data register reads. The
input buffer for the associated pin is always enabled unless the pin is enabled as an
analog function.
When a shared digital function is enabled for a pin, the output buffer is controlled by the
shared function. However, the data direction register bit still controls the source for reads
of the port data register.
When a shared analog function is enabled for a pin, both the input and output buffers
are disabled. A value of 0 is read for any port data bit where the bit is an input (PTxDDn
= 0) and the input buffer is disabled. In general, whenever a pin is shared with both an
alternate digital function and an analog function, the analog function has priority such that
if both the digital and analog functions are enabled, the analog function controls the pin.
It is a good programming practice to write to the port data register before changing the
direction of a port pin to become an output. This ensures that the pin will not be driven
momentarily with an old data value that happened to be in the port data register.
An internal pullup device can be enabled for each port pin by setting the corresponding
bit in one of the pullup enable registers (PTxPEn). The pullup device is disabled if the
pin is configured as an output by the general purpose I/O control logic or any shared
peripheral function regardless of the state of the corresponding pullup enable register bit.
The pullup device is also disabled if the pin is controlled by an analog function.
8.1 Unused pin configuration
Any general purpose I/O pins which are not used in the application must be properly
configured to avoid a floating input that could cause excessive supply current, IDD
.
When the device comes out of the reset state the NXP supplied firmware will not
configure any of the general purpose I/O pins.
Recommended configuration methods are:
1. Configure the general purpose I/O pin as an input (PTxDDn = 0) with the pin
connected to the VDD source; use a pullup resistor of 10-51 kΩ to assure sufficient
noise immunity.
2. Configure the general purpose I/O pin as an input (PTxDDn = 0) with the internal
pullup activated (PTxPEn = 1) and leave the pin disconnected.
3. Configure the general purpose I/O pin as an output (PTxDDn = 1) and drive the pin
low (PTxDn = 0) and leave the pin disconnected.
In cases where GPIOs are directly connected to AVDD, VDD, AVSS, VSS or RVSS, user
application should configure the GPIO as an input with the internal pull-up disabled,
in order to prevent software code faults from causing excessive supply current states
should these pins become outputs.
FXTH87ERM
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
54 / 183
NXP [ NXP ]
