NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
6.9.1 FLASH clock divider register (FCDIV)
Bit 7 of this register is a read-only status flag. Bits 6 through 0 can be read at any time
but can be written only once. Before any erase or programming operations are possible,
write to this register to set the frequency of the clock for the nonvolatile memory system
within acceptable limits.
Table 14.ꢀFLASH clock divider register (FCDIV) (address $1820)
Bit
R
7
6
PRDIV8
0
5
DIV5
0
4
DIV4
0
3
DIV3
0
2
DIV2
0
1
DIV1
0
0
DIV0
0
W
Reset
0
= Reserved
Table 15.ꢀFCDIV register field descriptions
Field
Description
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has
been written since reset. Reset clears this bit and the first write to this register causes this bit to become
set regardless of the data written.
7
DIVLD
0ꢀFCDIV has not been written since reset; erase and program operations disabled for FLASH
1ꢀFCDIV has been written since reset; erase and program operations enabled for FLASH
Prescale (Divide) FLASH Clock by 8
6
0ꢀClock input to the FLASH clock divider is the bus rate clock
1ꢀClock input to the FLASH clock divider is the bus rate clock divided by 8
PRDIV8
Divisor for FLASH Clock Divider — The FLASH clock divider divides the bus rate clock (or the bus
rate clock divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV5:DIV0 field plus one. The resulting
frequency of the internal FLASH clock must fall within the range of 200 kHz to 150 kHz for proper FLASH
operations. Program/Erase timing pulses are one cycle of this internal FLASH clock which corresponds to
a range of 5 μs to 6.7 μs. The automated programming logic uses an integer number of these pulses to
complete an erase or program operation.
5:0
DIV[5:0]
• if PRDIV8 = 0 — fFCLK = fBUS ÷ ([DIV5:DIV0] + 1)
• if PRDIV8 = 1 — fFCLK = fBUS ÷ (8 × ([DIV5:DIV0] + 1))
Table 16 shows the appropriate values for PRDIV8 and DIV5:DIV0 for selected bus frequencies.
Table 16.ꢀFLASH clock divider settings
fBUS
PRDIV8
(Binary)
DIV5:DIV0
(Decimal)
fFCLK
Program/Erase Timing Pulse
(5 μs Min, 6.7 μs Max)
20 MHz
10ꢀMHz
8 MHz
1
0
0
0
0
0
0
12
49
39
19
9
192.3 kHz
200 kHz
200 kHz
200 kHz
200 kHz
200 kHz
200 kHz
5.2 μs
5 μs
5 μs
5 μs
5 μs
5 μs
5 μs
4 MHz
2 MHz
1ꢀMHz
200 kHz
4
0
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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