NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
4.4.6 XO, XI pins
The XO and XI pins are for an external crystal to be used by the internal PLL for creating
the carrier frequencies and data rates for the RF pin.
4.4.7 LF[A:B] pins
The LF[A:B] pins can be used by the LF receiver (LFR) as one differential input channel
for sensing low level signals from an external low frequency (LF) coil. The external LF
coil should be connected between the LFA and the LFB pins.
Signaling into the LFR pins can place the FXTH87E into various diagnostic or operational
modes. The LFR is comprised of the detector and the decoder.
Each LF[A:B] pin will always have an impedance of approximately 500 kΩ to VSS due to
the LFR input circuitry. The LFA/LFB pins are used by the LFR when the LFEN control bit
is set and are not functional when the LFEN control bit is clear.
4.4.8 PTA[1:0] pins
The PTA[1:0] pins are general purpose I/O pins. These two pins can be configured
as normal bidirectional I/O pins with programmable pullup or pulldown devices and/or
wakeup interrupt capability; or one or both can be connected to the two input channels
of the A/D converter module. The pulldown devices can only be activated if the wakeup
interrupt capability is enabled. User software must configure the general purpose I/O
pins so that they do not result in "floating" inputs as described in Section 8.1 "Unused pin
configuration" PTA[1:02] map to keyboard Interrupt function bits [1:0].
4.4.9 PTA[3:2] pins
The PTA[3:2] pins are general purpose I/O pin. These two pins can be configured as
normal bidirectional I/O pin with programmable pullup or pulldown devices and/or wakeup
interrupt capability; or one or both can be connected to the two input channels of the
Timer Pulse Width (TPM1) module. The pulldown devices can only be activated if the
wakeup interrupt capability is enabled. User software must configure the general purpose
I/O pins so that they do not result in "floating" inputs as described in Section 8.1 "Unused
pin configuration". PTA[3:2] map to keyboard Interrupt function bits [3:2].
4.4.10 BKGD/PTA4 pin
The BKGD/PTA4 pin is used to place the FXTH87E in the BACKGROUND DEBUG
mode (BDM) to evaluate MCU code and to also transfer data to/from the internal
memories. If the BKGD/PTA4 pin is held low when the FXTH87E comes out of a power-
on reset the device will go into the ACTIVE BACKGROUND DEBUG mode (BDM).
The BKGD/PTA4 pin has an internal pullup device and can connected to VDD in the
application unless there is a need to enter BDM operation after the device as been
soldered into the PWB. If in-circuit BDM is desired the BKGD/PTA4 pin can be left
unconnected, but should be connected to VDD through a low impedance resistor
(< 10 kΩ) which can be over-driven by an external signal. This low impedance resistor
reduces the possibility of getting into the debug mode in the application due to an EMC
event. When the BDM is disabled, PTA4 can be used as an output-only GPIO.
FXTH87ERM
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© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
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