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F87EHHD 参数 Datasheet PDF下载

F87EHHD图片预览
型号: F87EHHD
PDF下载: 下载PDF文件 查看货源
内容描述: [FXTH87E, Family of Tire Pressure Monitor Sensors]
分类和应用:
文件页数/大小: 183 页 / 1700 K
品牌: NXP [ NXP ]
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NXP Semiconductors  
FXTH87E  
FXTH87E, Family of Tire Pressure Monitor Sensors  
5.5 STOP Modes  
One of two stop modes are entered upon execution of a STOP instruction when the  
STOPE bit in the system option register is set. In all STOP modes, all internal clocks  
are halted except for the low frequency 1 kHz oscillator (LFO) which runs continuously  
whenever power is applied to the VDD and VSS pins. If the STOPE bit is not set when  
the CPU executes a STOP instruction, the MCU will not enter any of the STOP modes  
and an illegal opcode reset is forced. The STOP modes are selected by setting the  
appropriate bits in SPMSC2. Table 5 summarizes the behavior of the MCU in each of the  
STOP1 and STOP4 modes.  
5.5.1 STOP1 Mode  
The STOP1 mode provides the lowest possible standby power consumption by causing  
the internal circuitry of the MCU to be powered down.  
When the MCU is in STOP1 mode, all internal circuits that are powered from the voltage  
regulator are turned off. The voltage regulator is in a low-power standby state. STOP1 is  
exited by asserting either a reset or an interrupt function to the MCU.  
Entering STOP1 mode automatically asserts LVD. STOP1 cannot be exited until the VDD  
is greater than VLVDH or VLV/DL rising (VDD must rise above the LVI re-arm voltage).  
Upon wakeup from STOP1 mode, the MCU will start up as from a power-on reset (POR)  
by taking the reset vector.  
Note: If there are any pending interrupts that have yet to be serviced then the device will  
not go into the STOP1 mode. Be certain that all interrupt flags have been cleared before  
entry to STOP1 mode.  
5.5.2 STOP4 LVD enabled in STOP mode  
The LVD system is capable of generating either an interrupt or a reset when the supply  
voltage drops below the LVD voltage. If the LVD is enabled by setting the LVDE and the  
LVDSE bits in SPMSC1 when the CPU executes a STOP instruction, then the voltage  
regulator remains active during STOP mode. If the user attempts to enter the STOP1  
with the LVD enabled in STOP (LVDSE = 1), the MCU will enter STOP4 instead.  
Table 5.ꢀSTOP mode behavior  
Mode  
STOP1  
STOP4  
LFO Oscillator, PWU  
Always On and Clocking  
Free-Running Counter (FRC)  
Real-Time Interrupt (RTI)[1]  
MFO Oscillator [2]  
HFO Oscillator  
Optionally On and Clocking  
Always On if using LFO as Clock  
Optionally On  
Optionally On  
Off  
Off  
Off  
CPU  
Standby  
Standby  
On  
RAM  
Off  
Parameter Registers  
FLASH  
On  
Off  
Standby  
Off  
TPM1 2-Chan Timer/PWM  
Digital I/O  
Off  
Disabled  
Standby  
FXTH87ERM  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2019. All rights reserved.  
Reference manual  
Rev. 5.0 — 4 February 2019  
13 / 183  
 
 
 
 
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