Philips Semiconductors
Product specification
Quad 2-input AND gate
74HC08; 74HCT08
FEATURES
DESCRIPTION
• Complies with JEDEC standard no. 8-1A
The 74HC/HCT08 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A. The 74HC/HCT08 provide the 2-input
AND function.
• ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
• Specified from −40 to +85 °C and −40 to +125 °C.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
74HC08
74HCT08
11
tPHL/tPLH propagation delay nA, nB to nY
CL = 15 pF; VCC = 5 V
7
ns
pF
pF
CI
input capacitance
power dissipation capacitance per gate notes 1 and 2
3.5
10
3.5
20
CPD
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. For 74HC08: the condition is VI = GND to VCC
.
For 74HCT08: the condition is VI = GND to VCC − 1.5 V.
FUNCTION TABLE
INPUT
OUTPUT
nA
L
nB
nY
L
L
H
L
L
L
H
H
L
H
H
Note
1. H = HIGH voltage level;
L = LOW voltage level.
2003 Jul 25
2
NXP [ NXP ]
