NXP Semiconductors
74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
5.2 Pin description
Table 2.
Symbol
DSA
DSB
Q0 to Q7
GND
CP
MR
V
CC
Pin description
Pin
1
2
3, 4, 5, 6, 10, 11, 12, 13
7
8
9
14
Description
data input
data input
output
ground (0 V)
clock input (LOW-to-HIGH, edge-triggered)
master reset input (active LOW)
positive supply voltage
6. Functional description
Table 3.
Operating
modes
Reset (clear)
Shift
Function table
Input
MR
L
H
H
H
H
[1]
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q = lower case letters indicate the state of the referenced input one set-up time prior to the LOW-to-HIGH clock transition
↑
= LOW-to-HIGH clock transition
Output
CP
X
↑
↑
↑
↑
DSA
X
l
l
h
h
DSB
X
l
h
l
h
Q0
L
L
L
L
H
Q1 to Q7
L to L
q0 to q6
q0 to q6
q0 to q6
q0 to q6
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
V
I
<
−0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
−0.5
V < V
O
< V
CC
+ 0.5 V
Conditions
Min
−0.5
-
-
-
-
−50
−65
Max
+7
±20
±20
±25
50
-
+150
Unit
V
mA
mA
mA
mA
mA
°C
74HC_HCT164_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 2 February 2010
4 of 20
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