NXP Semiconductors
74HC164; 74HCT164
8-bit serial-in, parallel-out shift register
Table 7.
Dynamic characteristics
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF; test circuit see
Figure 10;
unless otherwise specified
Symbol Parameter
C
PD
power
dissipation
capacitance
Conditions
Min
per package;
V
I
= GND to V
CC
−
1.5 V
25
°C
Typ Max
40
-
-
−40 °C
to +85
°C
Min
-
Max
-
−40 °C
to +125
°C
Unit
Min
-
Max
-
pF
[1]
[2]
[3]
t
pd
is the same as t
PHL
and t
PLH
.
t
t
is the same as t
THL
and t
TLH
.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μW):
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
1/f
max
V
I
CP input
GND
V
M
t
W
t
PHL
V
OH
Qn output
V
OL
V
Y
V
M
V
X
t
PLH
t
THL
t
TLH
001aal392
(1) Measurement points are given in
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 7.
Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency
Measurement points
Input
V
M
0.5V
CC
1.3 V
Output
V
M
0.5V
CC
1.3 V
V
X
0.1V
CC
0.1V
CC
V
Y
0.9V
CC
0.9V
CC
Table 8.
Type
74HC164
74HCT164
74HC_HCT164_4
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 04 — 2 February 2010
9 of 20
PHILIPS [ NXP SEMICONDUCTORS ]
