Nano100(A)
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD = 1.8V@12MHz,
IIDLE8
0.7
mA
disable all IP and disable PLL
VDD = 3.6V@12MHz,
IIDLE9
IIDLE10
IIDLE11
IIDLE12
IIDLE13
IIDLE14
IIDLE15
4.5
0.7
4.2
0.7
1.7
0.6
1
mA
mA
mA
mA
mA
mA
mA
enable all IP and disable PLL
VDD = 3.6V@12MHz,
Operating Current
Idle Mode
disable all IP and disable PLL
@ IRC 12MHz,
HCLK = 12MHz
VDD = 1.8V@12MHz,
enable all IP and disable PLL
VDD = 1.8V@12MHz,
disable all IP and disable PLL
VDD = 3.6V@4MHz,
enable all IP and disable PLL
VDD = 3.6V@4MHz,
Operating Current
Idle Mode
disable all IP and disable PLL
@ XTAL 4MHz,
HCLK = 4MHz
VDD = 1.8V@4MHz,
enable all IP and disable PLL
VDD = 1.8V@4MHz,
IIDLE16
0.5
mA
disable all IP and disable PLL
VDD = 3.6V@ 32.768kHz
IIDLE17
IIDLE18
IIDLE19
85
75
70
uA
uA
uA
enable all IP and disable PLL
VDD = 3.6V@ 32.768kHz
Operating Current
Idle Mode
disable all IP and disable PLL
@ XTAL 32.768kHz,
HCLK = 32.768kHz
VDD = 1.8V@ 32.768kHz
enable all IP and disable PLL
VDD = 1.8V@ 32.768kHz
IIDLE20
65
uA
disable all IP and disable PLL
VDD = 3.6V@ 10kHz
IIDLE21
IIDLE22
IIDLE23
IIDLE24
IPWD1
80
75
65
63
1.5
uA
uA
uA
uA
A
enable all IP and disable PLL
VDD = 3.6V@ 10kHz
Operating Current
Idle Mode
disable all IP and disable PLL
@ IRC 10kHz,
HCLK = 10kHz
VDD = 1.8V@ 10kHz
enable all IP and disable PLL
VDD = 1.8V@ 10kHz
disable all IP and disable PLL
Standby Current
VDD = 3.6V, RTC OFF, all clock stop
With RAM Retenstion, IO no loading
Power-down Mode
Mar 31, 2015
Page 80 of 95
Revision V1.00
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