Nano100(A)
Pin No.
Pin Name
Type Description
LQFP
LQFP
LQFP
QFN
100-pin 64-pin
48-pin
33-pin
I2SDO
MOSI21
PC.7
O
O
I2S data output
SPI2 2nd MOSI (Master Out, Slave In) pin
Digital GPIO pin
I/O
I/O
I
AD5
EBI Address/Data bus bit5
Timer1 capture input
87
53
41
TC1
PWM0CH1
PC.6
O
PWM1 Channel1 output
Digital GPIO pin
I/O
I/O
I
AD4
EBI Address/Data bus bit4
Timer 0 capture input
SmartCard1 card detect pin
PWM0 Channel0 output
Digital GPIO pin
88
54
42
27
TC0
SC1CD
PWM0CH0
I
O
PC.15
I/O
User program must enable pull-up resistor in LQFP48
package.
89
55
AD3
I/O
I
EBI Address/Data bus bit3
Timer0 capture input
PWM1 Channel1 output
Digital GPIO pin
TC0
PWM1CH2
O
PC.14
I/O
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
90
91
56
57
AD2
I/O
I/O
I/O
I
EBI Address/Data bus bit2
PWM1 Channel3 output
Digital GPIO pin
PWM1CH3
PB.15
43
28
nINT1
External interrupt1 input pin
Snooper pin
SNOOPER
I
92
93
58
59
44
45
29
30
XT1_OUT
XT1_IN
O
I
External 4~24 MHz crystal output pin
External 4~24 MHz crystal input pin
External reset input: Low active, set this pin low reset chip
to initial state. With internal pull-up.
94
95
96
60
61
62
46
31
nRESET
VSS
I
P
P
Ground
Power supply for I/O ports and LDO source for internal PLL
and digital circuit
VDD
Digital GPIO pin
97
PF.4
I/O
User program must enable pull-up resistor in LQFP64 and
LQFP48 package.
Mar 31, 2015
Page 38 of 95
Revision V1.00
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