M58LT256JST, M58LT256JSB
Bus operations
3.5
Standby
Standby disables most of the internal circuitry allowing a substantial reduction of the current
consumption. The memory is in standby when Chip Enable and Reset are at V . The power
IH
consumption is reduced to the standby level I
and the outputs are set to high impedance,
DD3
independently from the Output Enable or Write Enable inputs. If Chip Enable switches to V
during a program or erase operation, the device enters standby mode when finished.
IH
3.6
Reset
During reset mode the memory is deselected and the outputs are high impedance. The
memory is in reset mode when Reset is at V . The power consumption is reduced to the
IL
reset level, independently from the Chip Enable, Output Enable or Write Enable inputs. If
Reset is pulled to V during a program or erase, this operation is aborted and the memory
SS
content is no longer valid.
(1)
Table 3.
Bus operations
Operation
E
G
W
L
RP
WAIT(2)
DQ15-DQ0
(3)
Bus read
VIL
VIL
VIL
VIL
VIH
X
VIL
VIH
X
VIH
VIL
VIH
VIH
X
VIL
VIL
VIH
VIH
VIH
VIH
VIH
VIL
Data output
(3)
Bus write
Data input
Address latch
Output disable
Standby
VIL
Data output or Hi-Z(4)
VIH
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Reset
X
X
1. X = ‘don't care’.
2. WAIT signal polarity is configured using the Set Configuration Register command.
3. L can be tied to VIH if the valid address has been previously latched.
4. Depends on G.
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NUMONYX [ NUMONYX B.V ]
