Signal descriptions
M58LT256JST, M58LT256JSB
2.7
Latch Enable (L)
Latch Enable latches the address bits on its rising edge. The address latch is transparent
when Latch Enable is at V and it is inhibited when Latch Enable is at V .
IL
IH
2.8
Clock (K)
The clock input synchronizes the memory to the microcontroller during synchronous read
operations; the address is latched on a Clock edge (rising or falling, according to the
configuration settings) when Latch Enable is at V . Clock is ignored during asynchronous
IL
read and in write operations.
2.9
Wait (WAIT)
Wait is an output signal used during synchronous read to indicate whether the data on the
output bus are valid. This output is high impedance when Chip Enable is at V , Output
IH
Enable is at V or Reset is at V . It can be configured to be active during the wait cycle or
IH
IL
one clock cycle in advance.
2.10
2.11
2.12
VDD supply voltage
V
provides the power supply to the internal core of the memory device. It is the main
DD
power supply for all operations (read, program and erase).
VDDQ supply voltage
V
provides the power supply to the I/O pins and enables all outputs to be powered
DDQ
independently from V
.
DD
VPP program supply voltage
V
is both a control input and a power supply pin. The two functions are selected by the
PP
voltage range applied to the pin.
If V is kept in a low voltage range (0 V to V
) V is seen as a control input. In this case
PP
DDQ
PP
a voltage lower than V
gives absolute protection against program or erase, while V in
PPLK
PP
the V
range enables these functions (see Tables 20 and 21, DC Characteristics for the
PP1
relevant values). V is only sampled at the beginning of a program or erase; a change in its
PP
value after the operation has started does not have any effect and program or erase
operations continue.
If V is in the range of V
it acts as a power supply pin. In this condition V must be
PP
PP
PPH
stable until the program/erase algorithm is completed.
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NUMONYX [ NUMONYX B.V ]
