Bus operations
M58LT256JST, M58LT256JSB
3
Bus operations
There are six standard bus operations that control the device. These are bus read, bus
write, address latch, output disable, standby and reset. See Table 3: Bus operations for a
summary.
Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the
memory and do not affect bus write operations.
3.1
Bus read
Bus read operations output the contents of the memory array, the electronic signature, the
Status Register and the common Flash interface. Both Chip Enable and Output Enable must
be at V to perform a read operation. The Chip Enable input should be used to enable the
IL
device. Output Enable should be used to gate data onto the output. The data read depends
on the previous command written to the memory (see Section 4: Command interface). See
Figures 9, 10 and 11 Read AC waveforms, and Tables 22 and 23 Read AC characteristics
for details of when the output becomes valid.
3.2
Bus write
Bus write operations write commands to the memory or latch input data to be programmed.
A bus write operation is initiated when Chip Enable and Write Enable are at V with Output
IL
Enable at V . Commands, input data and addresses are latched on the rising edge of Write
IH
Enable or Chip Enable, whichever occurs first. The addresses must be latched prior to the
write operation by toggling Latch Enable (when Chip Enable is at V ). The Latch Enable
IL
must be tied to V during the bus write operation.
IH
See Figures 15 and 16, Write AC waveforms, and Tables 24 and 25, Write AC
characteristics for details of the timing requirements.
3.3
3.4
Address latch
Address latch operations input valid addresses. Both Chip enable and Latch Enable must be
at V during address latch operations. The addresses are latched on the rising edge of
IL
Latch Enable.
Output disable
The outputs are high impedance when the Output Enable is at V .
IH
16/108
NUMONYX [ NUMONYX B.V ]
